x86 – 中英文维基百科词条融合

By cathayvista芯片（集成电路）

本文基于英文词条的线索，并补充部分来自中文词条的内容。辽观搬运时进行了必要的合规化处理，以使其能够在中国内地上传。
中文词条参见链接（无法从中国内地访问）：点击这里访问。
英文词条原文链接（无法从中国内地访问）：点击这里访问。

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辽观提供的翻译仅供参考。辽观提供的翻译仅供参考。文中可能包含无法从中国内地访问的链接。

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1. 正文（发布于知乎专栏）

请点击这里访问

2. 参见（维基百科的相关词条）

3. 参考文献

3.1 英文词条引用列表

  1. ·  Pryce, Dave (May 11, 1989). “80486 32-bit CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN” (Press release). 
  2. ·  Rao, P.V.S. (2009). Computer System Architecture. Prentice-Hall of India. p. 402 (Section 19.1, The x86 family of processors). ISBN 978-81-203-3594-3. 
  3. ·  Mhatre, Swapneel Chandrakant (2012). Microprocessors and Interfacing Techniques: For S. E. (Computer Engineering) Semester II of University of Pune. Jaico Publishing House. ISBN 978-81-8495-325-1. 
  4. ·  Alcorn, Paul (February 9, 2022). “AMD Sets All-Time CPU Market Share Record as Intel Gains in Desktop and Notebook PCs”. Tom’s Hardware. 
  5. ·  Brandon, Jonathan (April 15, 2015). “The cloud beyond x86: How old architectures are making a comeback”. ICloud PE. Business Cloud News. Archived from the original on August 19, 2021. Retrieved November 23, 2020. Despite the dominance of x86 in the datacentre it is difficult to ignore the noise vendors have been making over the past couple of years around non-x86 architectures like ARM… 
  6. ·  “June 2022”. TOP500. 
  7. ·  Larabel, Michael (May 30, 2022). “AMD-Powered Frontier Supercomputer Tops Top500 At 1.1 Exaflops, Tops Green500 Too”. Phoronix. Retrieved June 1, 2022. 
  8. ·  Dvorak, John C. “Whatever Happened to the Intel iAPX432?”. Dvorak.org. Archived from the original on November 25, 2017. Retrieved April 18, 2014. 
  9. ·  iAPX 286 Programmer’s Reference (PDF). Intel. 1983. Archived (PDF) from the original on August 28, 2017. Retrieved August 28, 2017. 
  10. ·  iAPX 86, 88 User’s Manual (PDF). Intel. August 1981. Archived (PDF) from the original on August 28, 2017. Retrieved August 28, 2017. 
  11. ·  Edwards, Benj (June 16, 2008). “Birth of a Standard: The Intel 8086 Microprocessor”. PCWorld. Archived from the original on September 26, 2010. Retrieved September 14, 2014. 
  12. ·  Stanley Mazor (January–March 2010). “Intel’s 8086”. IEEE Annals of the History of Computing. 32 (1): 75–79. doi:10.1109/MAHC.2010.22. S2CID 16451604. 
  13. ·  “AMD Discloses New Technologies At Microprocessor Forum” (Press release). AMD. October 5, 1999. Archived from the original on March 2, 2000. “Time and again, processor architects have looked at the inelegant x86 architecture and declared it cannot be stretched to accommodate the latest innovations,” said Nathan Brookwood, principal analyst, Insight 64. 
  14. ·  Burt, Jeff (April 5, 2010). “Microsoft to End Intel Itanium Support”. eWeek. Retrieved June 2, 2022. 
  15. ·  “Intel 64 and IA-32 Architectures Optimization Reference Manual” (PDF). Intel. September 2019. 3.4.2.2 Optimizing for Macro-fusion. Archived (PDF) from the original on February 14, 2020. Retrieved March 7, 2020. 
  16. ·  Fog, Agner. “The microarchitecture of Intel, AMD and VIA CPUs” (PDF). p. 107. Archived (PDF) from the original on March 22, 2019. Retrieved March 7, 2020. Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode. 
  17. ·  “Zet: The x86 (IA-32) open implementation: Overview”. OpenCores. November 4, 2013. Archived from the original on February 11, 2018. Retrieved January 5, 2014. 
  18. ·  “Zhaoxin Preparing Linux Kernel Support For 7-Series Centaur CPUs”. www.phoronix.com. Retrieved April 5, 2022. 
  19. ·  “Zhaoxin aiming at 2021 release for its 7nm x86 CPUs – CPU – News – HEXUS.net”. m.hexus.net. Retrieved April 5, 2022. 
  20. ·  “Zhaoxin Finally Adding “Lujiazui” x86_64 CPU Tuning To GCC”. www.phoronix.com. Retrieved April 5, 2022. 
  21. ·  “Setup and installation considerations for Windows x64 Edition-based computers”. Archived from the original on September 11, 2014. Retrieved September 14, 2014. 
  22. ·  “Envisioning a Simplified Intel Architecture”. Intel. 
  23. ·  Larabel, Michael (May 20, 2023). “Intel Publishes “X86-S” Specification For 64-bit Only Architecture”. Phoronix. Retrieved May 20, 2023. 
  24. ·  “Processors — What mode of addressing do the Intel Processors use?”. Archived from the original on September 11, 2014. Retrieved September 14, 2014. 
  25. ·  “DSB Switches”. Intel VTune Amplifier 2013. Intel. Archived from the original on December 2, 2013. Retrieved August 26, 2013. 
  26. ·  “The 8086 Family User’s Manual” (PDF). Intel Corporation. October 1979. p. 2-68. Archived (PDF) from the original on April 4, 2018. Retrieved March 28, 2018. 
  27. ·  “iAPX 286 Programmer’s Reference Manual” (PDF). Intel Corporation. 1983. 2.4.3 Memory Addressing Modes. Archived (PDF) from the original on August 28, 2017. Retrieved August 28, 2017. 
  28. ·  80386 Programmer’s Reference Manual (PDF). Intel Corporation. 1986. 2.5.3.2 EFFECTIVE-ADDRESS COMPUTATION. Archived (PDF) from the original on December 28, 2018. Retrieved March 28, 2018. 
  29. ·  Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture. Intel Corporation. March 2018. Chapter 3. Archived from the original on January 26, 2012. Retrieved March 19, 2014. 
  30. ·  Andriesse, Dennis (2019). “6.5 Effects of Compiler Settings on Disassembly”. Practical binary analysis: build your own Linux tools for binary instrumentation, analysis, and disassembly. San Francisco, CA: No Starch Press, Inc. ISBN 978-1-59327-913-4. OCLC 1050453850. 
  31. ·  “Guide to x86 Assembly”. Cs.virginia.edu. September 11, 2013. Archived from the original on March 24, 2020. Retrieved February 6, 2014. 
  32. ·  “FSTSW/FNSTSW — Store x87 FPU Status Word”. Archived from the original on January 25, 2022. Retrieved January 15, 2020. The FNSTSW AX form of the instruction is used primarily in conditional branching… 
  33. ·  Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture (PDF). Intel. March 2013. Chapter 8. Archived (PDF) from the original on April 2, 2013. Retrieved April 23, 2013. 
  34. ·  “Intel 80287 family”. CPU-world. Archived from the original on August 9, 2016. Retrieved July 21, 2016. 
  35. ·  Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture (PDF). Intel. March 2013. Chapter 9. Archived (PDF) from the original on April 2, 2013. Retrieved April 23, 2013. 
  36. ·  Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture (PDF). Intel. March 2013. Chapter 10. Archived (PDF) from the original on April 2, 2013. Retrieved April 23, 2013. 
  37. ·  iAPX 286 Programmer’s Reference (PDF). Intel. 1983. Section 1.2, “Modes of Operation”. Archived (PDF) from the original on August 28, 2017. Retrieved January 27, 2014. 
  38. ·  iAPX 286 Programmer’s Reference (PDF). Intel. 1983. Chapter 6, “Memory Management and Virtual Addressing”. Archived (PDF) from the original on August 28, 2017. Retrieved January 27, 2014. 
  39. ·  “Intel’s Yamhill Technology: x86-64 compatible |Geek.com”. Archived from the original on September 5, 2012. Retrieved July 18, 2008. 
  40. ·  “Programming With the Intel MMX™ Technology”. Embedded Pentium® Processor Family Technical Information Center. Intel. Archived from the original on July 25, 2003. Retrieved June 5, 2022. 
  41. ·  Krishnaprasad, S. (January 1, 2004). “SIMD programming illustrated using Intel’s MMX instruction set”. Journal of Computing Sciences in Colleges. 19 (3): 268–277. ISSN 1937-4771. 
  42. ·  Sexton, Michael Justin Allen (April 21, 2017). “The History Of AMD CPUs”. Tom’s Hardware. Retrieved June 5, 2022. 
  43. ·  Shimpi, Anand Lal (October 29, 1998). “AMD’s K6-2 350: Something to do…” AnandTech. Retrieved June 5, 2022. 
  44. ·  “Intel’s MMX and AMD’s 3DNow! SIMD Operations”. web.mit.edu. Retrieved June 5, 2022. 
  45. ·  “3DNow!™ Technology Manual” (PDF). Advanced Micro Devices. Retrieved June 5, 2022. 
  46. ·  “Upgrading And Repairing PCs 21st Edition: Processor Features”. Tom’s Hardware. October 31, 2013. Retrieved June 5, 2022. 
  47. ·  AMD, Inc. (February 2002). “Appendix E” (PDF). AMD Athlon™ Processor x86 Code Optimization Guide (Revision K ed.). p. 250. Archived (PDF) from the original on April 13, 2017. Retrieved April 13, 2017. A 2-bit index consisting of PCD and PWT bits of the page table entry is used to select one of four PAT register fields when PAE (page address extensions) is enabled, or when the PDE doesn’t describe a large page. 
  48. ·  Manek Dubash (July 20, 2006). “Will Intel abandon the Itanium?”. Techworld. Archived from the original on February 19, 2011. Retrieved December 19, 2010. Once touted by Intel as a replacement for the x86 product line, expectations for Itanium have been throttled well back. 
  49. ·  “IBM WebSphere Application Server 64-bit Performance Demystified” (PDF). IBM Corporation. September 6, 2007. p. 14. Archived (PDF) from the original on January 25, 2022. Retrieved April 9, 2010. Figures 5, 6 and 7 also show the 32-bit version of WAS runs applications at full native hardware performance on the POWER and x86-64 platforms. Unlike some 64-bit processor architectures, the POWER and x86-64 hardware does not emulate 32-bit mode. Therefore applications that do not benefit from 64-bit features can run with full performance on the 32-bit version of WebSphere running on the above mentioned 64-bit platforms. 
  50. ·  “Volume 2: System Programming” (PDF). AMD64 Architecture Programmer’s Manual. AMD Corporation. September 2012. Archived (PDF) from the original on February 22, 2014. Retrieved February 17, 2014. 
  51. ·  Charlie Demerjian (September 26, 2003). “Why Intel’s Prescott will use AMD64 extensions”. The Inquirer. Archived from the original on October 10, 2009. Retrieved October 7, 2009. 
  52. ·  Adams, Keith; Agesen, Ole (October 21–25, 2006). A Comparison of Software and Hardware Techniques for x86 Virtualization (PDF). Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, 2006. ACM 1-59593-451-0/06/0010. Archived (PDF) from the original on August 20, 2010. Retrieved December 22, 2006. 
  53. ·  Winkel, Sebastian; Agron, Jason. “Advanced Performance Extensions (APX)”. Intel. Retrieved October 22, 2023. 
  54. ·  Robinson, Dan. “Intel adds fresh x86 and vector instructions for future chips”. The Register. Retrieved October 22, 2023. 
  55. ·  Bonshor, Gavin. “Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures”. AnandTech. Retrieved October 22, 2023. 
  56. ·  Alcorn, Paul. “Intel’s New AVX10 Brings AVX-512 Capabilities to E-Cores”. Tom’s Hardware. Retrieved October 22, 2023. 
  57. ·  Shah, Agam. “Intel’s Generational On-Chip Change APX Will Make All the Apps Faster”. The New Stack. Retrieved October 22, 2023. 
  58. ·  Byrne, Joseph. “APX is Biggest x86 Addition Since 64 Bits”. Tech Insights. 
  59. ·  Larabel, Michael. “Intel APX Code Begins Landing Within The GCC Compiler”. Phoronix. Retrieved October 22, 2023. 
  60. ·  “Intel® Advanced Performance Extensions (Intel® APX) Architecture Specification”. Intel. July 21, 2023. Retrieved October 22, 2023.

3.2 英文词条延伸阅读（Further Reading)

Rosenblum, Mendel; Garfinkel, Tal (May 2005). “Virtual machine monitors: current technology and future trends”. IEEE Computer. 38 (5): 39–47. CiteSeerX10.1.1.614.9870. doi:10.1109/MC.2005.176. S2CID10385623.

3.3 中文词条

  1. Rust, Adamson. AMD bans use of Hammer word, X86-64. The Inquirer. 2003-04-24 [2010-10-30]. （原始内容存档于2009-10-12）.

4. 外部链接

维基共享资源中相关的多媒体资源：X86
Wikimedia Commons has media related to X86 architecture.

Wikibooks has a book on the topic of: X86 Assembly/X86 Architecture

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