RISC-V – 中英文维基百科词条融合

By cathayvista开源运动, 芯片（集成电路）

本文基于英文词条的线索，并补充部分来自中文词条的内容。辽观搬运时进行了必要的合规化处理，以使其能够在中国内地上传。
中文词条参见链接（无法从中国内地访问）：点击这里访问。
英文词条原文链接（无法从中国内地访问）：点击这里访问。

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1. 正文（发布于知乎专栏）

请点击这里访问

2. 参见（维基百科的相关词条，无法从中国内地访问）

3. 参考文献

3.1 英文词条引用列表

  1. ·  Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
  2. ·  Waterman, Andrew; Asanović, Krste, eds. (December 2019). “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213” (PDF). RISC-V Foundation. Retrieved 5 November 2021.
  3. ·  Waterman, Andrew; Asanović, Krste (3 December 2021). “The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203” (PDF). RISC-V International. Retrieved 5 November 2021.
  4. ·  Urquhart, Roddy (29 March 2021). “What Does RISC-V Stand For? A brief history of the open ISA”. Systems & Design: Opinion. Semiconductor Engineering.
  5. ·  Waterman, Andrew; Asanović, Krste (7 May 2017). “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2” (PDF). RISC-V International. Retrieved 5 November 2021.
  6. ·  Newsome, Tim; Wachs, Megan (22 March 2019). “RISC-V External Debug Support Version 0.13.2 d5029366d59e8563c08b6b9435f82573b603e48e” (PDF). RISC-V International. Retrieved 7 November 2021.
  7. ·  “Contributors”. riscv.org. Regents of the University of California. Archived from the original on 7 September 2018. Retrieved 25 August 2014.
  8. ·  “About RISC-V, RISC-V International is the global non-profit home of the open standard RISC-V Instruction Set Architecture (ISA)”. RISC-V International.
  9. ·  “RISC-V To Move HQ to Switzerland Amid Trade War Concerns”. EE Times Europe. 28 November 2019.
  10. ·  Demerjian, Chuck (7 August 2013). “A long look at how ARM licenses chips: Part 1”. SemiAccurate.
  11. ·  Demerjian, Chuck (8 August 2013). “How ARM licenses its IP for production: Part 2”. SemiAccurate.
  12. ·  “Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning”. 15 November 2019.
  13. ·  Asanović, Krste. “Instruction Sets Should be Free” (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 15 November 2016.
  14. ·  “Rocket Core Generator”. RISC-V. Regents of the University of California. Archived from the original on 6 October 2014. Retrieved 1 October 2014.
  15. ·  Celio, Christopher; Love, Eric. “riscv-sodor: educational microarchitectures for risc-v isa”. GitHub. Regents of the University of California. Retrieved 25 October 2019.
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  18. ·  Waterman, Andrew; Asanović, Krste (31 May 2016). “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.1” (PDF). University of California, Berkeley. EECS-2016-118. Retrieved 5 November 2021.
  19. ·  Patterson, David A.; Ditzel, David R. (October 1980). “The Case for the Reduced Instruction Set Computer”. ACM SIGARCH Computer Architecture News. 8 (6): 25. doi:10.1145/641914.641917. S2CID 12034303.
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  21. ·  “ARM4U”. OpenCores. Retrieved 26 August 2014.
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  23. ·  Samples, Alan Dain; Klein, Mike; Foley, Pete (1985). SOAR Architecture (Technical report). University of California, Berkeley. UCB/CSD-85-226.
  24. ·  Hill, Mark Donald; et al. (Susan J. Eggers, James Richard Larus, George S. Taylor, Glenn D. Adams, Bidyut Kumar Bose, Garth A. Gibson, Paul Mark Hansen, John Keller, Shing I. Kong, Corinna Grace Lee, Daebum Lee, J. M. Pendleton, Scott Allen Ritchie, David A. Wood, Benjamin G. Zorn, Paul N. Hilfinger, D. A. Hodges, Randy H. Katz, John K. Ousterhout, and David A. Patterson) (December 1985). SPUR: A VLSI Multiprocessor Workstation (Technical report). University of California, Berkeley. UCB/CSD-86-273.
  25. ·  Asanović, Krste. “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA” (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 13 May 2011.
  26. ·  Hruska, Joel (21 August 2014). “RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source”. ExtremeTech.
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  28. ·  “A new blueprint for microprocessors challenges the industry’s giants”. The Economist. 3 October 2019. ISSN 0013-0613. Retrieved 10 November 2019.
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  30. ·  “Members”. RISC-V International. Retrieved 1 August 2023.
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  36. ·  “Vector Extension”. RISC-V International. November 2021.
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  39. ·  RISC-V Platform Horizontal Subcommittee (December 2021). “RISC-V Platform Specification” (PDF). Version 0.3-draft.
  40. ·  Waterman, Andrew (13 May 2011). Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed. U.C. Berkeley: Regents of the University of California. p. 32. Retrieved 25 August 2014.
  41. ·  Waterman, Andrew; et al. “The RISC-V Compressed Instruction Set Manual Version 1.9 (draft)” (PDF). RISC-V. Retrieved 18 July 2016.
  42. ·  Brussee, Rogier. “A Complete 16-bit RVC”. Google Groups. RISC-V Foundation. Retrieved 18 July 2019.
  43. ·  Brussee, Rogier. “Proposal: Xcondensed, [a] … Compact … 16 bit standalone G-ISA”. RISC-V ISA Mail Server. Google Groups. Retrieved 10 November 2016.
  44. ·  Phung, Xan. “Improved Xcondensed”. Google Groups. RISC-V Foundation. Retrieved 18 July 2019.
  45. ·  Ionescu, Liviu. “The RISC-V Microcontroller Profile”. GitHub. Retrieved 5 April 2018.
  46. ·  Barros, Cesar (1 April 2018). “Proposal: RV16E”. RISC-V ISA Developers (Mailing list). Retrieved 2 April 2018.
  47. ·  Bonzini, Paolo; Waterman, Andrew. “Proposal for Virtualization without H mode”. RISC-V ISA Developers (Mailing list). Retrieved 24 February 2017.
  48. ·  Wolf, Claire, ed. (10 January 2021). “RISC-V Bitmanip Extension Document Version 0.93” (PDF). GitHub. RISC-V Foundation. Retrieved 9 March 2021.
  49. ·  “Instruction Summary for a “P” ISA Proposal”. Google Groups. ANDES Technologies. Retrieved 13 January 2020.
  50. ·  Su, Charlie (30 June 2018). “Comprehensive RISC-V Solutions for AIoT” (PDF). RISC-V Content. RISC-V Foundation. Retrieved 28 January 2023.
  51. ·  Schmidt, Colin; Ou, Albert; Lee, Yunsup; Asanović, Krste. “RISC-V Vector Extension Proposal” (PDF). RISC-V. Regents of the University of California. Retrieved 14 March 2016.
  52. ·  “Release Vector Extension 1.0, frozen for public review · riscv/Riscv-v-spec”. GitHub.
  53. ·  Ou, Albert; Nguyen, Quan; Lee, Yunsup; Asanović, Krste. “A Case for MVPs: Mixed-Precision Vector Processors” (PDF). UC Berkeley EECS. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.
  54. ·  Lee, Yunsup; Grover, Vinod; Krashinsky, Ronny; Stephenson, Mark; Keckler, Stephen W.; Asanović, Krste. “Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures” (PDF). Berkeley’s EECS Site. Regents of the University of California. Archived from the original (PDF) on 15 March 2016. Retrieved 14 March 2016.
  55. ·  Bradbury, Alex; Wallentowitz, Stefan. “RISC-V Run Control Debug”. Google Docs. RISC-V Foundation. Retrieved 20 January 2017.
  56. ·  Newsome, Tim. “RISC-V Debug Group > poll results”. Google Groups, RISC-V Debug Group. RISC-V Foundation. Retrieved 20 January 2017.
  57. ·  McGooganus. “riscv-trace-spec”. GitHub. Retrieved 13 January 2020.
  58. ·  Dahad, Nitin. “UltraSoC Tackles RISC-V Support Challenge by Donating Trace Encoder”. EE Times. Aspencore. Retrieved 13 January 2020.
  59. ·  “RISC-V Cores and SoC Overview”. RISC-V. 25 September 2019. Retrieved 5 October 2019.
  60. ·  “D1”. Retrieved 30 September 2021.
  61. ·  “RISC-V International Members”. RISC-V International. Retrieved 22 January 2021.
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  63. ·  “CloudBEAR”. Retrieved 16 October 2018.
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  66. ·  “3.6.2 Ultra-Low-Power Co-Processor”. ESP32-S2 Family Datasheet V1.1 (PDF). Espressif Systems. 2020. Retrieved 9 June 2020.
  67. ·  “ESP32-C3 Family Datasheet V0.4” (PDF). Espressif Systems. 2020. Retrieved 27 December 2020.
  68. “Introducing ESP32-C3”. Espressif (Press release). 27 November 2020.
  69. ·  Manners, David (8 June 2021). “Fraunhofer licensing fault-tolerant RISC core for safety-critical applications”. Electronics Weekly. Retrieved 13 April 2022.
  70. ·  “GigaDevice Unveils The GD32V Series With RISC-V Core in a Brand New 32-bit General Purpose Microcontroller”. www.gigadevice.com. 23 August 2019. Archived from the original on 29 August 2019. Retrieved 29 August 2019.
  71. ·  “Sipeed Longan Nano – RISC-V GD32VF103CBT6 Development Board”. www.seeedstudio.com. Retrieved 29 August 2019.
  72. ·  Kleidermacher, Dave; Seed, Jesse; Barbello, Brandon (27 October 2021). “Pixel 6: Setting a new standard for mobile security”. Google Security Blog. Archived from the original on 27 October 2021. Retrieved 12 February 2023.
  73. ·  “GreenWaves GAP8 is a Low Power RISC-V IoT Processor Optimized for Artificial Intelligence Applications”. CNXSoft: Embedded Systems News. 27 February 2018. Retrieved 4 March 2018.
  74. ·  Yoshida, Junko (26 February 2018). “AI Comes to Sensing Devices”. EE Times. Retrieved 10 July 2018.
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  76. ·  “IMG RTXM-2200 CPU”. Imagination. Retrieved 30 September 2023.
  77. ·  Leibson, Steven (9 January 2023). “MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un”. EEJournal.
  78. ·  Robinson, Dan (11 May 2022). “MIPS discloses first RISC-V chips coming in Q4 2022”. The Register.
  79. ·  Shilov, Anton (9 December 2020). “Seagate Develops Own RISC-V Cores for Storage Controllers”. Tom’s Hardware.
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  81. ·  SiFive. “Hi-Five1: Open-source Arduino-Compatible Development Kit”. Crowd Supply. Retrieved 2 December 2016.
  82. ·  “FU540 SoC CPU”. SiFive. Archived from the original on 5 October 2018. Retrieved 24 October 2018.
  83. ·  Horwitz, Josh (23 March 2023). “Chinese search giant Baidu invests in RISC-V chip technology startup StarFive”. Reuters.
  84. ·  Sharwood, Simon (27 March 2023). “Chinese web giant Baidu backs RISC-V for the datacenter”. The Register.
  85. ·  “Syntacore”. Retrieved 11 December 2018.
  86. ·  “SCR1 is a high-quality open-source RISC-V MCU core in Verilog”. GitHub. Syntacore. Retrieved 13 January 2020.
  87. ·  “RISC-V workshop proceedings”. 11 December 2016. Retrieved 28 January 2023.
  88. ·  “WinChipHead (WCH)”.
  89. ·  “CH32V003”. WCH-IC. Retrieved 10 July 2023.
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  91. ·  Manners, David (23 November 2016). “Codasip and UltraSoC Combine on RISC-V”. Electronics Weekly. Metropolis International Group, Ltd. Retrieved 23 November 2016.
  92. ·  Desikan, Shubashree (6 August 2018). “IIT-Madras powers up a desi chip”. The Hindu. ISSN 0971-751X. Retrieved 25 September 2020.
  93. ·  “Meet India’s Atmanirbhar Microprocessor chip ‘Moushik’, meant for IoT devices”. WION. Retrieved 25 September 2020.
  94. ·  Ashenden, Peter (9 November 2016). “Re: [isa-dev] RISC V ISA for embedded systems”. RISC-V ISA Developers (Mailing list). Retrieved 10 November 2016. At ASTC (www.astc-design.com), we have an implementation of RV32EC as a synthesizable IP core intended for small embedded applications, such as smart sensors and IoT.
  95. ·  “C-DAC announces Tech Conclave 2019”. The Times of India. Archived from the original on 17 May 2019. Retrieved 12 April 2019.
  96. ·  Sharwood, Simon (19 August 2020). “India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit”. The Register. Retrieved 9 July 2021.
  97. ·  “VEGA MICROPROCESSORS”. Vega Processor – CDAC. 9 July 2021. Archived from the original on 9 July 2021. Retrieved 9 July 2021.
  98. ·  “NOEL-V Processor”. Cobham Gaisler. Retrieved 14 January 2020.
  99. ·  “FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed”. 4 February 2016.
  100. ·  “Esperanto exits stealth mode, aims at AI with a 4,096 core 7nm RISC-V monster”. wikichip.org. January 2018. Retrieved 2 January 2018.
  101. ·  “PULPino GitHub project”. GitHub. Retrieved 2 February 2018.
  102. ·  “PULP Platform”. PULP Platform. Retrieved 2 February 2018.
  103. ·  “Accelerator Stream”. European Processor Initiative (EPI). Retrieved 22 February 2020.
  104. ·  Redmond, Calista (28 January 2023). “How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing”. RISC-V International News. RISC-V International.
  105. ·  Halfacree, Gareth (10 June 2021). “RISC-V boffins lay out a plan for bringing the architecture to high-performance computing”. The Register. Retrieved 9 July 2021.
  106. ·  “IIT Madras Open Source Processor Project”. Rapid IO. IIT Madras. 26 August 2014. Archived from the original on 14 September 2014. Retrieved 13 September 2014.
  107. ·  “IIT Madras Develops and Boots up MOUSHIK Microprocessor for IoT Devices”. IIT Madras. 24 September 2020. Retrieved 9 July 2021.
  108. ·  “lowRISC website”. Retrieved 10 May 2015.
  109. ·  Xie, Joe (July 2016). NVIDIA RISC V Evaluation Story. 4th RISC-V Workshop. Youtube. Archived from the original on 13 November 2021.
  110. ·  “RV64X: A Free, Open Source GPU for RISC-V”. EETimes. Retrieved 9 February 2021.
  111. ·  Frumusanu, Andrei (30 October 2019). “SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP”. Anandtech.
  112. ·  “Esperanto ET-SoC-1 1092 RISC-V AI Accelerator Solution at Hot Chips 33”. 24 August 2021.
  113. ·  Gwennap, Linley (13 December 2021). “Ventana Develops RISC-V Chiplet”. Microprocessor Report.
  114. ·  Dahad, Nitin (6 September 2021). “RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute”. EE Times.
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  116. ·  Celio, Christopher. “riscv-boom”. GitHub. Regents of the University of California. Retrieved 29 March 2020.
  117. ·  Wolf, Claire. “PicoRV32 – A Size-Optimized RISC-V CPU”. GitHub. Retrieved 27 February 2020.
  118. ·  “MIPT-MIPS: Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs”. GitHub.
  119. ·  “MIPS syscall functions available in MARS”. courses.missouristate.edu. Retrieved 28 May 2023.
  120. ·  Kindgren, Olof. “SERV – The serial RISC-V CPU”. GitHub. Retrieved 25 September 2023.
  121. ·  Kindgren, Olof (29 December 2022). “SERV: 32-bit is the New 8-bit” (Video, 2:38). YouTube. RISC-V Foundation. Retrieved 25 September 2023.
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  125. ·  Shilov, Anton. “Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative”. www.anandtech.com. Retrieved 23 May 2019.
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  130. ·  “Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910”. 20 October 2021. Retrieved 20 October 2021.
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3.2 中文词条引用列表

  1. ·  RISC-V讀卡器：開放式架構地圖集第1期 1st. Strawberry Canyon. ISBN 978-0999249109.)
  2. ·  新浪-图灵奖得主加入清华，牵头推动芯片开源
  3. ·  Celio, Christopher. ucb-bar/riscv-sodor. Regents of the University of California. [12 February 2015]. （原始内容存档于2018-06-11）.
  4. ·  Celio, Christopher. CS 152 Laboratory Exercise 3 (PDF). Regents of the University of California. [12 February 2015]. （原始内容 (PDF)存档于2016-06-23）.
  5. ·  詳細了解ARM許可芯片的方法：第1部分. SemiAccurate. 2013 [2017-08-28]. （原始内容存档于2017-08-24）.
  6. ·  精簡指令集計算機的案例. ACM SIGARCH计算机体系结构新闻. 1980年10月, 8 (6): 25. doi:10.1145/641914.641917.
  7. ·  https://riscv.org/members/. [2021-05-01]. （原始内容存档于2021-04-26）. 缺少或|title=为空 (帮助)
  8. ·  U.S.-based chip-tech group moving to Switzerland over trade curb fears. Reuters. 2019-11-26 [2019-11-26]. （原始内容存档于2022-04-28） （英语）.
  9. ·  RISC-V History – RISC-V International. RISC-V International. [2020-05-14]. （原始内容存档于2020-04-15）.
  10. ·  Krste Asanović, David A. Patterson. Instruction Sets Should Be Free: The Case For RISC-V (PDF). U.C. Berkeley Technical Reports. [2018-10-31]. （原始内容存档 (PDF)于2019-04-23）.
  11. ·  Waterman, Andrew; Asanović, Krste. The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2 (PDF). RISC-V International. 7 May 2017 [5 November 2021]. （原始内容存档 (PDF)于2023-04-13）.
  12. ·  Waterman, Andrew; Asanović, Krste. The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203 (PDF). RISC-V International. 3 December 2021 [5 November 2021].
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4. 延伸阅读 Further Reading

Library resources about RISC-V（关于RISC-V的库资源）
Resources in your library Resources in other libraries

5. 外部链接

Wikimedia Commons has media related to RISC-V.（维基共享资源有与RISC-V相关的媒体。）

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