{"id":2273,"date":"2023-12-07T10:10:04","date_gmt":"2023-12-07T02:10:04","guid":{"rendered":"https:\/\/cathayvista.top\/?p=2273"},"modified":"2025-01-31T13:58:55","modified_gmt":"2025-01-31T05:58:55","slug":"risc-v-zhen","status":"publish","type":"post","link":"https:\/\/cathayvista.top\/index.php\/2023\/12\/07\/risc-v-zhen\/","title":{"rendered":"RISC-V &#8211; \u4e2d\u82f1\u6587\u7ef4\u57fa\u767e\u79d1\u8bcd\u6761\u878d\u5408"},"content":{"rendered":"\n<blockquote class=\"wp-block-quote is-layout-flow wp-block-quote-is-layout-flow\">\n<p class=\"has-small-font-size\">\u672c\u6587\u57fa\u4e8e\u82f1\u6587\u8bcd\u6761\u7684\u7ebf\u7d22\uff0c\u5e76\u8865\u5145\u90e8\u5206\u6765\u81ea\u4e2d\u6587\u8bcd\u6761\u7684\u5185\u5bb9\u3002\u8fbd\u89c2\u642c\u8fd0\u65f6\u8fdb\u884c\u4e86\u5fc5\u8981\u7684\u5408\u89c4\u5316\u5904\u7406\uff0c\u4ee5\u4f7f\u5176\u80fd\u591f\u5728\u4e2d\u56fd\u5185\u5730\u4e0a\u4f20\u3002 <br>\u4e2d\u6587\u8bcd\u6761\u53c2\u89c1\u94fe\u63a5\uff08\u65e0\u6cd5\u4ece\u4e2d\u56fd\u5185\u5730\u8bbf\u95ee\uff09\uff1a<a href=\"https:\/\/zh.wikipedia.org\/wiki\/RISC-V\" target=\"_blank\" rel=\"noreferrer noopener\">\u70b9\u51fb\u8fd9\u91cc\u8bbf\u95ee<\/a>\u3002 <br>\u82f1\u6587\u8bcd\u6761\u539f\u6587\u94fe\u63a5\uff08\u65e0\u6cd5\u4ece\u4e2d\u56fd\u5185\u5730\u8bbf\u95ee\uff09\uff1a<a href=\"https:\/\/en.wikipedia.org\/wiki\/RISC-V\" target=\"_blank\" rel=\"noreferrer noopener\">\u70b9\u51fb\u8fd9\u91cc\u8bbf\u95ee<\/a>\u3002<\/p>\n\n\n\n<p class=\"has-small-font-size\"><a href=\"https:\/\/link.zhihu.com\/?target=https%3A\/\/cathayvista.top\/index.php\/2023\/06\/25\/wei2-ji1-bai3-ke1\/\" target=\"_blank\" rel=\"noreferrer noopener\">\u7ef4\u57fa\u767e\u79d1\uff08Wikipedia\uff09\u662f\u7f8e\u56fd\u7ef4\u57fa\u5a92\u4f53\u57fa\u91d1\u4f1a\u7684\u4e92\u8054\u7f51\u767e\u79d1\u9879\u76ee<\/a>\uff0c\u5176\u5185\u5bb9\u53ef\u80fd\u53d7\u5230\u7acb\u573a\u3001\u4fe1\u606f\u6765\u6e90\u7b49\u56e0\u7d20\u5f71\u54cd\uff0c\u8bf7\u5ba2\u89c2\u770b\u5f85\u3002\u6b63\u6587\u5185\u5bb9\u4e0d\u4ee3\u8868\u8bd1\u8005\u89c2\u70b9\u3002 \u8fbd\u89c2\u63d0\u4f9b\u7684\u7ffb\u8bd1\u4ec5\u4f9b\u53c2\u8003\u3002<strong>\u6587\u4e2d\u53ef\u80fd\u5305\u542b\u65e0\u6cd5\u4ece\u4e2d\u56fd\u5185\u5730\u8bbf\u95ee\u7684\u94fe\u63a5\u3002<\/strong><\/p>\n<cite>\u8fbd\u89c2\u642c\u8fd0\u3001\u7ffb\u8bd1\u3001\u6574\u5408\u7684\u4e2d\u82f1\u6587\u7ef4\u57fa\u767e\u79d1\u8bcd\u6761\uff0c\u4e0e\u539f\u7ef4\u57fa\u767e\u79d1\u8bcd\u6761\u540c\u6837\u9075\u5faa<a href=\"https:\/\/zhuanlan.zhihu.com\/p\/653887754\" target=\"_blank\" rel=\"noreferrer noopener\">CC-BY-SA 4.0\u534f\u8bae<\/a>\uff0c\u5728\u7b26\u5408\u534f\u8bae\u8981\u6c42\u7684\u60c5\u51b5\u4e0b\u60a8\u53ef\u4ee5\u514d\u8d39\u4f7f\u7528\u5176\u5185\u5bb9\uff08\u5305\u62ec\u5546\u7528\uff09\u3002 \u56fe\u7247\u548c\u89c6\u9891\u53ef\u80fd\u9075\u5faa\u4e0d\u540c\u7684\u534f\u8bae\uff0c\u8be6\u89c1<a href=\"https:\/\/zhuanlan.zhihu.com\/p\/666846485\" target=\"_blank\" rel=\"noreferrer noopener\">\u672c\u6587\u6d89\u53ca\u7684\u5171\u4eab\u534f\u8bae<\/a><\/cite><\/blockquote>\n\n\n\n<h2 class=\"wp-block-heading\">1. \u6b63\u6587\uff08\u53d1\u5e03\u4e8e\u77e5\u4e4e\u4e13\u680f\uff09<\/h2>\n\n\n\n<p><a href=\"https:\/\/zhuanlan.zhihu.com\/p\/669733490\/\" data-type=\"link\" data-id=\"https:\/\/zhuanlan.zhihu.com\/p\/669733490\/\">\u8bf7\u70b9\u51fb\u8fd9\u91cc\u8bbf\u95ee<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">2. \u53c2\u89c1\uff08\u7ef4\u57fa\u767e\u79d1\u7684\u76f8\u5173\u8bcd\u6761\uff0c\u65e0\u6cd5\u4ece\u4e2d\u56fd\u5185\u5730\u8bbf\u95ee\uff09<\/h2>\n\n\n\n<ul class=\"has-small-font-size wp-block-list\">\n<li class=\"has-small-font-size\"><a href=\"https:\/\/en.wikipedia.org\/wiki\/List_of_open-source_computing_hardware\">List of open-source computing hardware<\/a>\uff08\u5f00\u6e90\u8ba1\u7b97\u786c\u4ef6\u5217\u8868\uff09<\/li>\n\n\n\n<li class=\"has-small-font-size\"><a href=\"https:\/\/en.wikipedia.org\/wiki\/Microprocessor_chronology\">Microprocessor chronology<\/a>\uff08\u5fae\u5904\u7406\u5668\u5e74\u8868\uff09<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/zh.wikipedia.org\/wiki\/%E7%B2%BE%E7%AE%80%E6%8C%87%E4%BB%A4%E9%9B%86\">\u7cbe\u7b80\u6307\u4ee4\u96c6<\/a> (RISC)<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/zh.wikipedia.org\/w\/index.php?title=OpenRISC&amp;action=edit&amp;redlink=1\">OpenRISC<\/a>\uff0c\u4ee5<a href=\"https:\/\/zh.wikipedia.org\/wiki\/GNU%E9%80%9A%E7%94%A8%E5%85%AC%E5%85%B1%E8%AE%B8%E5%8F%AF%E8%AF%81\">GNU General Public License<\/a>\u6388\u6743<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/zh.wikipedia.org\/w\/index.php?title=OVPsim&amp;action=edit&amp;redlink=1\">OVPsim<\/a>\uff0cRISC-V\u5904\u7406\u5668\u6307\u4ee4\u5b50\u96c6\u3001\u5185\u6838\u548c\u7cfb\u7edf\u7684\u6307\u4ee4\u7cbe\u786e\u6a21\u62df\u5668\u3002\u514d\u8d39\u4e3a\u975e\u5546\u4e1a\u7528\u9014\u63d0\u4f9b\u3002<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/zh.wikipedia.org\/wiki\/ARM%E6%9E%B6%E6%A7%8B\">ARM\u67b6\u6784<\/a><\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/zh.wikipedia.org\/w\/index.php?title=%E5%BC%80%E6%BA%90%E8%BF%90%E7%AE%97%E7%A1%AC%E4%BB%B6%E5%88%97%E8%A1%A8&amp;action=edit&amp;redlink=1\">\u5f00\u6e90\u8fd0\u7b97\u786c\u4ef6\u5217\u8868<\/a><\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">3. \u53c2\u8003\u6587\u732e<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">3.1 \u82f1\u6587\u8bcd\u6761\u5f15\u7528\u5217\u8868<\/h3>\n\n\n\n<ol class=\"has-small-font-size wp-block-list\">\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_A._Patterson_(computer_scientist)\">Patterson, David A.<\/a> (6 August 2014). <a href=\"http:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2014\/EECS-2014-146.pdf\">Instruction Sets Should Be Free: The Case For RISC-V<\/a> (PDF). EECS Department, University of California, Berkeley. UCB\/EECS-2014-146.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Waterman, Andrew; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>, eds. (December 2019). <a href=\"https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/download\/Ratified-IMAFDQC\/riscv-spec-20191213.pdf\">&#8220;The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213&#8221;<\/a> (PDF). RISC-V Foundation. Retrieved 5 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (3 December 2021). <a href=\"https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/download\/Priv-v1.12\/riscv-privileged-20211203.pdf\">&#8220;The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203&#8221;<\/a> (PDF). RISC-V International. Retrieved 5 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Urquhart, Roddy (29 March 2021). <a href=\"https:\/\/semiengineering.com\/what-does-risc-v-stand-for\/\">&#8220;What Does RISC-V Stand For? A brief history of the open ISA&#8221;<\/a>. Systems &amp; Design: Opinion. Semiconductor Engineering.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Waterman, Andrew; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (7 May 2017). <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2017\/05\/riscv-spec-v2.2.pdf\">&#8220;The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2&#8221;<\/a> (PDF). RISC-V International. Retrieved 5 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Newsome, Tim; Wachs, Megan (22 March 2019). <a href=\"https:\/\/github.com\/riscv\/riscv-debug-spec\/blob\/release\/riscv-debug-release.pdf\">&#8220;RISC-V External Debug Support Version 0.13.2 d5029366d59e8563c08b6b9435f82573b603e48e&#8221;<\/a> (PDF). RISC-V International. Retrieved 7 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20180907044920\/https:\/riscv.org\/contributors\/\">&#8220;Contributors&#8221;<\/a>. riscv.org. Regents of the University of California. Archived from <a href=\"https:\/\/riscv.org\/contributors\/\">the original<\/a> on 7 September 2018. Retrieved 25 August 2014.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/riscv.org\/about\/\">&#8220;About RISC-V, RISC-V International is the global non-profit home of the open standard RISC-V Instruction Set Architecture (ISA)&#8221;<\/a>. RISC-V International.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.eetimes.eu\/risc-v-to-move-hq-to-switzerland-amid-trade-war-concerns\/\">&#8220;RISC-V To Move HQ to Switzerland Amid Trade War Concerns&#8221;<\/a>. EE Times Europe. 28 November 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Demerjian, Chuck (7 August 2013). <a href=\"https:\/\/semiaccurate.com\/2013\/08\/07\/a-long-look-at-how-arm-licenses-chips\/\">&#8220;A long look at how ARM licenses chips: Part 1&#8221;<\/a>. SemiAccurate.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Demerjian, Chuck (8 August 2013). <a href=\"https:\/\/semiaccurate.com\/2013\/08\/08\/how-arm-licenses-its-ip-for-production\/\">&#8220;How ARM licenses its IP for production: Part 2&#8221;<\/a>. SemiAccurate.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.hackster.io\/news\/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0\">&#8220;Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning&#8221;<\/a>. 15 November 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>. <a href=\"https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2014\/EECS-2014-146.pdf\">&#8220;Instruction Sets Should be Free&#8221;<\/a> (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 15 November 2016.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20141006085238\/https:\/riscv.org\/download.html#tab_rocket\">&#8220;Rocket Core Generator&#8221;<\/a>. RISC-V. Regents of the University of California. Archived from <a href=\"https:\/\/riscv.org\/download.html#tab_rocket\">the original<\/a> on 6 October 2014. Retrieved 1 October 2014.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Celio, Christopher; Love, Eric. <a href=\"https:\/\/github.com\/ucb-bar\/riscv-sodor\">&#8220;riscv-sodor: educational microarchitectures for risc-v isa&#8221;<\/a>. GitHub. Regents of the University of California. Retrieved 25 October 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/shakti.org.in\">&#8220;SHAKTI Processor Program&#8221;<\/a>. Indian Institute of Technology Madras. Retrieved 3 September 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Celio, Christopher. <a href=\"https:\/\/web.archive.org\/web\/20150212211808\/http:\/www-inst.eecs.berkeley.edu\/~cs152\/sp14\/handouts\/lab3.pdf\">&#8220;CS 152 Laboratory Exercise 3&#8221;<\/a> (PDF). UC Berkeley. Regents of the University of California. Archived from <a href=\"http:\/\/www-inst.eecs.berkeley.edu\/~cs152\/sp14\/handouts\/lab3.pdf\">the original<\/a> (PDF) on 12 February 2015. Retrieved 12 February 2015.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (31 May 2016). <a href=\"https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-118.pdf\">&#8220;The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.1&#8221;<\/a> (PDF). University of California, Berkeley. EECS-2016-118. Retrieved 5 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">Patterson, David A.<\/a>; Ditzel, David R. (October 1980). &#8220;The Case for the Reduced Instruction Set Computer&#8221;. ACM SIGARCH Computer Architecture News. <strong>8<\/strong> (6): 25. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Doi_(identifier)\">doi<\/a>:<a href=\"https:\/\/doi.org\/10.1145%2F641914.641917\">10.1145\/641914.641917<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/S2CID_(identifier)\">S2CID<\/a>&nbsp;<a href=\"https:\/\/api.semanticscholar.org\/CorpusID:12034303\">12034303<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"http:\/\/opencores.org\/project,amber\">&#8220;Amber ARM-compatible core&#8221;<\/a>. OpenCores. Retrieved 26 August 2014.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"http:\/\/opencores.org\/project,arm4u\">&#8220;ARM4U&#8221;<\/a>. OpenCores. Retrieved 26 August 2014.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Chen, Tony; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">David A. Patterson<\/a> (24 January 2016). <a href=\"http:\/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-6.html\">RISC-V Geneology<\/a> (Technical report). University of California at Berkeley. UCB\/EECS-2016-6.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Samples, Alan Dain; Klein, Mike; Foley, Pete (1985). <a href=\"http:\/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/1985\/5940.html\">SOAR Architecture<\/a> (Technical report). University of California, Berkeley. UCB\/CSD-85-226.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Hill, Mark Donald; et&nbsp;al. (Susan J. Eggers, James Richard Larus, George S. Taylor, Glenn D. Adams, Bidyut Kumar Bose, Garth A. Gibson, Paul Mark Hansen, John Keller, Shing I. Kong, Corinna Grace Lee, Daebum Lee, J. M. Pendleton, Scott Allen Ritchie, David A. Wood, Benjamin G. Zorn, Paul N. Hilfinger, D. A. Hodges, Randy H. Katz, John K. Ousterhout, and <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">David A. Patterson<\/a>) (December 1985). <a href=\"http:\/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/1985\/6083.html\">SPUR: A VLSI Multiprocessor Workstation<\/a> (Technical report). University of California, Berkeley. UCB\/CSD-86-273.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>. <a href=\"https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2011\/EECS-2011-62.pdf\">&#8220;The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA&#8221;<\/a> (PDF). U.C. Berkeley Technical Reports. Regents of the University of California. Retrieved 13 May 2011.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Hruska, Joel (21 August 2014). <a href=\"https:\/\/www.extremetech.com\/computing\/188405-risc-rides-again-new-risc-v-architecture-hopes-to-battle-arm-and-x86-by-being-totally-open-source\">&#8220;RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source&#8221;<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/ExtremeTech\">ExtremeTech<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/riscv.org\/about\/history\/\">&#8220;RISC-V History&#8221;<\/a>. Retrieved 28 January 2023.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.economist.com\/science-and-technology\/2019\/10\/03\/a-new-blueprint-for-microprocessors-challenges-the-industrys-giants\">&#8220;A new blueprint for microprocessors challenges the industry&#8217;s giants&#8221;<\/a>. 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Retrieved 14 May 2020.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20190410201639\/https:\/riscv.org\/risc-v-foundation\/\">&#8220;RISC-V Foundation&#8221;<\/a>. RISC-V Foundation. Archived from <a href=\"https:\/\/riscv.org\/risc-v-foundation\/\">the original<\/a> on 10 April 2019. Retrieved 15 March 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"http:\/\/linleygroup.com\/press_detail.php?The-Linley-Group-Announces-Winners-of-Annual-Analysts-Choice-Awards-85\">&#8220;The Linley Group Announces Winners of Annual Analysts&#8217; Choice Awards&#8221;<\/a> (Press release). The Linley Group. 12 January 2017. Retrieved 21 January 2018.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/github.com\/riscv\/riscv-bitmanip\/releases\/download\/1.0.0\/bitmanip-1.0.0-38-g865e7a7.pdf\">&#8220;Bit-Manipulation ISA-extensions&#8221;<\/a> (PDF). RISC-V International. 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At ASTC (www.astc-design.com), we have an implementation of RV32EC as a synthesizable IP core intended for small embedded applications, such as smart sensors and IoT.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20190517221350\/https:\/timesofindia.indiatimes.com\/home\/education\/news\/c-dac-announces-tech-conclave-2019\/articleshow\/68650294.cms\">&#8220;C-DAC announces Tech Conclave 2019&#8221;<\/a>. The Times of India. Archived from <a href=\"https:\/\/timesofindia.indiatimes.com\/home\/education\/news\/c-dac-announces-tech-conclave-2019\/articleshow\/68650294.cms\">the original<\/a> on 17 May 2019. Retrieved 12 April 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Sharwood, Simon (19 August 2020). <a href=\"https:\/\/www.theregister.com\/2020\/08\/19\/india_microprocessor_challenge_risc_v\/\">&#8220;India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit&#8221;<\/a>. The Register. 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Retrieved 14 January 2020.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/freebsdfoundation.blogspot.be\/2016\/02\/initial-freebsd-risc-v-architecture.html\">&#8220;FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed&#8221;<\/a>. 4 February 2016.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/fuse.wikichip.org\/news\/686\/esperanto-exits-stealth-mode-aims-at-ai-with-a-4096-core-7nm-risc-v-monster\/\">&#8220;Esperanto exits stealth mode, aims at AI with a 4,096 core 7nm RISC-V monster&#8221;<\/a>. wikichip.org. January 2018. Retrieved 2 January 2018.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/github.com\/pulp-platform\/pulpino\">&#8220;PULPino GitHub project&#8221;<\/a>. GitHub. Retrieved 2 February 2018.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/pulp-platform.org\/\">&#8220;PULP Platform&#8221;<\/a>. PULP Platform. Retrieved 2 February 2018.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/www.european-processor-initiative.eu\/accelerator\/\">&#8220;Accelerator Stream&#8221;<\/a>. European Processor Initiative (EPI). Retrieved 22 February 2020.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Redmond, Calista (28 January 2023). <a href=\"https:\/\/riscv.org\/news\/2019\/08\/how-the-european-processor-initiative-is-leveraging-risc-v-for-the-future-of-supercomputing\/\">&#8220;How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing&#8221;<\/a>. RISC-V International News. RISC-V International.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Halfacree, Gareth (10 June 2021). <a href=\"https:\/\/www.theregister.com\/2021\/06\/10\/riscv_hpc\/\">&#8220;RISC-V boffins lay out a plan for bringing the architecture to high-performance computing&#8221;<\/a>. The Register. Retrieved 9 July 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20140914001234\/http:\/www.rapidio.org\/2014\/08\/iit-madras-open-source-processor-project\/\">&#8220;IIT Madras Open Source Processor Project&#8221;<\/a>. Rapid IO. IIT Madras. 26 August 2014. Archived from <a href=\"http:\/\/www.rapidio.org\/2014\/08\/iit-madras-open-source-processor-project\/\">the original<\/a> on 14 September 2014. Retrieved 13 September 2014.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.iitm.ac.in\/happenings\/press-releases-and-coverages\/iit-madras-develops-and-boots-moushik-microprocessor-iot\">&#8220;IIT Madras Develops and Boots up MOUSHIK Microprocessor for IoT Devices&#8221;<\/a>. IIT Madras. 24 September 2020. Retrieved 9 July 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"http:\/\/www.lowrisc.org\/\">&#8220;lowRISC website&#8221;<\/a>. Retrieved 10 May 2015.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Xie, Joe (July 2016). <a href=\"https:\/\/www.youtube.com\/watch?v=gg1lISJfJI0\">NVIDIA RISC V Evaluation Story<\/a>. 4th RISC-V Workshop. Youtube. <a href=\"https:\/\/ghostarchive.org\/varchive\/youtube\/20211113\/gg1lISJfJI0\">Archived<\/a> from the original on 13 November 2021.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/www.eetimes.com\/rv64x-a-free-open-source-gpu-for-risc-v\/\">&#8220;RV64X: A Free, Open Source GPU for RISC-V&#8221;<\/a>. EETimes. Retrieved 9 February 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Frumusanu, Andrei (30 October 2019). <a href=\"https:\/\/www.anandtech.com\/show\/15036\/sifive-announces-first-riscv-ooo-cpu-core-the-u8series-processor-ip\">&#8220;SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP&#8221;<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Anandtech\">Anandtech<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/www.servethehome.com\/esperanto-et-soc-1-1092-risc-v-ai-accelerator-solution-at-hot-chips-33\">&#8220;Esperanto ET-SoC-1 1092 RISC-V AI Accelerator Solution at Hot Chips 33&#8221;<\/a>. 24 August 2021.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Gwennap, Linley (13 December 2021). &#8220;Ventana Develops RISC-V Chiplet&#8221;. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Microprocessor_Report\">Microprocessor Report<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Dahad, Nitin (6 September 2021). <a href=\"https:\/\/www.eetimes.com\/risc-v-chiplet-startup-raises-38m-targets-data-center-compute\/\">&#8220;RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute&#8221;<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/EE_Times\">EE Times<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>; et&nbsp;al. <a href=\"https:\/\/github.com\/ucb-bar\/rocket-chip\">&#8220;rocket-chip&#8221;<\/a>. GitHub. RISC-V International. Retrieved 11 November 2016.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Celio, Christopher. <a href=\"https:\/\/github.com\/riscv-boom\/riscv-boom\">&#8220;riscv-boom&#8221;<\/a>. GitHub. Regents of the University of California. Retrieved 29 March 2020.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Wolf, Claire. <a href=\"https:\/\/github.com\/cliffordwolf\/picorv32\">&#8220;PicoRV32 &#8211; A Size-Optimized RISC-V CPU&#8221;<\/a>. GitHub. Retrieved 27 February 2020.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/github.com\/MIPT-ILab\/mipt-mips\/\">&#8220;MIPT-MIPS: Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs&#8221;<\/a>. GitHub.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/courses.missouristate.edu\/KenVollmar\/mars\/Help\/SyscallHelp.html\">&#8220;MIPS syscall functions available in MARS&#8221;<\/a>. courses.missouristate.edu. Retrieved 28 May 2023.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Kindgren, Olof. <a href=\"https:\/\/github.com\/olofk\/serv\">&#8220;SERV &#8211; The serial RISC-V CPU&#8221;<\/a>. GitHub. Retrieved 25 September 2023.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Kindgren, Olof (29 December 2022). <a href=\"https:\/\/www.award-winning.me\/serv-32-bit-is-the-new-8-bit\/\">&#8220;SERV: 32-bit is the New 8-bit&#8221;<\/a> (Video, 2:38). YouTube. RISC-V Foundation. Retrieved 25 September 2023.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Halfacree, Gareth (14 June 2022). <a href=\"https:\/\/fossi-foundation.org\/blog\/2022-06-14-ecl51#corescore-benchmark-sees-new-record-with-10000-risc-v-cores-on-one-fpga\">&#8220;CoreScore Benchmark Sees New Record with 10,000 RISC-V Cores on One FPGA&#8221;<\/a>. fossi-foundation.org. FOSSi Foundation. Retrieved 25 September 2023.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Traber, Andreas; et&nbsp;al. <a href=\"https:\/\/www.pulp-platform.org\/\">&#8220;PULP: Parallel Ultra Low Power&#8221;<\/a>. ETH Zurich, University of Bologna. Retrieved 5 August 2016.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Shilov, Anton. <a href=\"https:\/\/www.anandtech.com\/show\/15231\/western-digital-rollsout-two-new-swerv-riscv-cores\">&#8220;Western Digital Rolls-Out Two New SweRV RISC-V Cores For Microcontrollers&#8221;<\/a>. www.anandtech.com. Retrieved 9 February 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Shilov, Anton. <a href=\"https:\/\/www.anandtech.com\/show\/13678\/western-digital-reveals-swerv-risc-v-core-and-omnixtend-coherency-tech\">&#8220;Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative&#8221;<\/a>. www.anandtech.com. Retrieved 23 May 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/abopen.com\/news\/western-digital-releases-swerv-risc-v-core-source-code\/\">&#8220;Western Digital Releases SweRV RISC-V Core Source Code&#8221;<\/a>. AB Open. 28 January 2019. <a href=\"https:\/\/web.archive.org\/web\/20190521224239\/https:\/abopen.com\/news\/western-digital-releases-swerv-risc-v-core-source-code\/\">Archived<\/a> from the original on 21 May 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/github.com\/chipsalliance\/Cores-SweRV\">Cores-SweRV<\/a> on <a href=\"https:\/\/en.wikipedia.org\/wiki\/GitHub\">GitHub<\/a><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Nolting, Stephan (2022). <a href=\"https:\/\/github.com\/stnolting\/neorv32\">&#8220;neorv32&#8221;<\/a>. GitHub. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Doi_(identifier)\">doi<\/a>:<a href=\"https:\/\/doi.org\/10.5281%2Fzenodo.7030070\">10.5281\/zenodo.7030070<\/a>. Retrieved 9 September 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.techspot.com\/news\/81177-china-alibaba-making-16-core-25-ghz-risc.html\">&#8220;China&#8217;s Alibaba is making a 16-core, 2.5 GHz RISC-V processor&#8221;<\/a>. www.techspot.com. 28 July 2019. Retrieved 30 July 2019.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/www.cnx-software.com\/2021\/10\/20\/alibaba-open-source-risc-v-cores-xuantie-e902-e906-c906-and-c910\/\">&#8220;Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910&#8221;<\/a>. 20 October 2021. Retrieved 20 October 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/github.com\/OpenXiangShan\/XiangShan\">XiangShan<\/a> repository on Github<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/www.cnx-software.com\/2021\/07\/05\/xiangshan-open-source-64-bit-risc-v-processor-rival-arm-cortex-a76\/\">XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76<\/a> &#8211; CNX Software<\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/wiki.freebsd.org\/riscv\">&#8220;riscv &#8211; FreeBSD Wiki&#8221;<\/a>. wiki.freebsd.org.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Montezelo, Manuel. <a href=\"https:\/\/groups.google.com\/a\/groups.riscv.org\/forum\/#!msg\/sw-dev\/u4VcUtB9r94\/4HiFYBhXAAAJ\">&#8220;Debian GNU\/Linux port for RISC-V 64&#8221;<\/a>. Google Groups. Retrieved 19 July 2018.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/fedoraproject.org\/wiki\/Architectures\/RISC-V\">&#8220;Architectures\/RISC-V&#8221;<\/a>. Fedora Wiki. Red Hat. Retrieved 26 September 2016.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.haiku-os.org\/blog\/kallisti5\/2021-11-07_booting_our_risc-v_images\/\">&#8220;Booting our RISC-V images&#8221;<\/a>. Haiku Project. 7 November 2021. Retrieved 4 March 2023.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Begari, Padmarao. <a href=\"https:\/\/groups.google.com\/a\/groups.riscv.org\/forum\/#!topic\/sw-dev\/j63wzz2ylY8\">&#8220;U-Boot port on RISC-V 32-bit is available&#8221;<\/a>. Google Groups. Microsemi. Retrieved 15 February 2017.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<a href=\"https:\/\/github.com\/HewlettPackard\/RiscVEdk2\">RiscVEdk2<\/a> on <a href=\"https:\/\/en.wikipedia.org\/wiki\/GitHub\">GitHub<\/a><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Almatary, Hesham. <a href=\"https:\/\/docs.sel4.systems\/Hardware\/RISCV.html\">&#8220;RISC-V, seL4&#8221;<\/a>. seL4 Documentation. Commonwealth Scientific and Industrial Research Organisation (CSIRO). Retrieved 13 July 2018.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Almatary, Hesham. <a href=\"https:\/\/github.com\/heshamelmatary\">&#8220;heshamelmatary&#8221;<\/a>. GitHub. Retrieved 13 July 2018.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/hex-five.com\/first-secure-iot-stack-riscv\/\">&#8220;MultiZone Secure IoT Stack, the First Secure IoT Stack for RISC-V&#8221;<\/a>. Hex Five Security. Hex Five Security, Inc. 22 February 2019. Retrieved 3 March 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/sourceforge.net\/projects\/rtospharos\/\">&#8220;Pharos&#8221;<\/a>. SourceForge. Retrieved 1 April 2020.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/web.archive.org\/web\/20181111215351\/https:\/riscv.org\/software-tools\/riscv-angel\/\">&#8220;ANGEL is a Javascript RISC-V ISA (RV64) Simulator that runs riscv-linux with BusyBox&#8221;<\/a>. RISCV.org. Archived from <a href=\"https:\/\/riscv.org\/software-tools\/riscv-angel\/\">the original<\/a> on 11 November 2018. Retrieved 17 January 2019.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Lee, Yunsup (5 March 2014). <a href=\"https:\/\/live-risc-v.pantheonsite.io\/2014\/03\/boot-risc-v-linux-in-your-web-browser\/\">&#8220;Boot RISC-V Linux in your web browser!&#8221;<\/a>. RISC-V International. Retrieved 4 September 2020.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20201201124529\/http:\/riscv.org.s3-website-us-west-1.amazonaws.com\/angel\/index.html\">&#8220;ANGEL \u2013 RISC-V&#8221;<\/a>. riscv.org.s3-website-us-west-1.amazonaws.com. Archived from <a href=\"http:\/\/riscv.org.s3-website-us-west-1.amazonaws.com\/angel\/index.html\">the original<\/a> on 1 December 2020. Retrieved 4 September 2020.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/wiki.qemu.org\/Documentation\/Platforms\/RISCV\">&#8220;Documentation\/Platforms\/RISCV&#8221;<\/a>. QEMU Wiki. Retrieved 7 May 2020.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Pu\u00f1al, Elias; Mateos, Alejandro Calderon (23 July 2021). <a href=\"https:\/\/zenodo.org\/record\/5130302\">CREATOR: Simulador did\u00e1ctico y gen\u00e9rico para la programaci\u00f3n en ensamblador<\/a> [CREATOR: Didactic and generic simulator for assembly programming]. XXXI Jornadas de Paralelismo (JP20\/21) (in Spanish). Malaga. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Doi_(identifier)\">doi<\/a>:<a href=\"https:\/\/doi.org\/10.5281%2Fzenodo.5130302\">10.5281\/zenodo.5130302<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (October 2021). <a href=\"https:\/\/ieeexplore.ieee.org\/document\/9640144\">A new generic simulator for the teaching of assembly programming<\/a>. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). Cartago, Costa Rica: IEEE (published 21 December 2021). pp.&nbsp;1\u20139. <a href=\"https:\/\/en.wikipedia.org\/wiki\/Doi_(identifier)\">doi<\/a>:<a href=\"https:\/\/doi.org\/10.1109%2FCLEI53233.2021.9640144\">10.1109\/CLEI53233.2021.9640144<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/ISBN_(identifier)\">ISBN<\/a>&nbsp;<a href=\"https:\/\/en.wikipedia.org\/wiki\/Special:BookSources\/978-1-6654-9503-5\">978-1-6654-9503-5<\/a>. <a href=\"https:\/\/en.wikipedia.org\/wiki\/S2CID_(identifier)\">S2CID<\/a>&nbsp;<a href=\"https:\/\/api.semanticscholar.org\/CorpusID:245387555\">245387555<\/a>. Retrieved 2 August 2022.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; CREATOR Web with RISC-V example: <a href=\"https:\/\/creatorsim.github.io\/creator\/?example_set=default_rv&amp;example=e12\">https:\/\/creatorsim.github.io\/creator\/?example_set=default_rv&amp;example=e12<\/a><\/li>\n\n\n\n<li>\u00b7&nbsp; CREATOR source code on GitHub: <a href=\"https:\/\/github.com\/creatorsim\/creator\">https:\/\/github.com\/creatorsim\/creator<\/a><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/wepsim.github.io\/wepsim\/ws_dist\/wepsim-classic.html?mode=ep&amp;examples_set=Default-RISCV&amp;example=14&amp;simulator=assembly:registers&amp;notify=false\">&#8220;WepSIM with RISC-V_im example&#8221;<\/a>. WepSIM.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/wepsim.github.io\/\">&#8220;WepSIM homepage&#8221;<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/chisel.eecs.berkeley.edu\/\">&#8220;Chisel: Constructing Hardware in a Scala Embedded Language&#8221;<\/a>. UC Berkeley. Regents of the University of California. Retrieved 12 February 2015.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/codasip.com\/codasip-studio\/\">&#8220;Codasip Studio&#8221;<\/a>. Codasip. Retrieved 19 February 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/github.com\/riscv\/riscv-compliance\">riscv\/riscv-compliance<\/a>, RISC-V, 12 February 2021, retrieved 19 February 2021<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.lauterbach.com\/frames.html?bdmriscv.html\">&#8220;RISC-V Debugger&#8221;<\/a>. www.lauterbach.com TRACE32 Debugger for RISC-V.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.sifive.com\/press\/lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores\">&#8220;Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores&#8221;<\/a>. www.sifive.com.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20220602223446\/https:\/www.lauterbach.com\/frames.html?news_514.html\">&#8220;TRACE32 supports SiFive&#8217;s RISC-V trace&#8221;<\/a>. www.lauterbach.com. Archived from <a href=\"https:\/\/www.lauterbach.com\/frames.html?news_514.html\">the original<\/a> on 2 June 2022. Retrieved 6 March 2021.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.segger.com\/news\/segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe\/\">&#8220;SEGGER Adds Support for SiFive&#8217;s Coreplex IP to Its Industry Leading J-Link Debug Probe&#8221;<\/a>. Retrieved 19 September 2017.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.segger.com\/news\/segger-embedded-studio-supports-risc-v-architecture\/\">&#8220;PR: SEGGER Embedded Studio supports RISC-V architecture&#8221;<\/a>. Retrieved 23 November 2017.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/www.segger.com\/news\/segger-presents-rtos-stacks-middleware-for-risc-v\/\">&#8220;PR: SEGGER presents RTOS, stacks, middleware for RISC-V&#8221;<\/a>. Retrieved 8 December 2017.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Dahad, Nitin (23 June 2020). <a href=\"https:\/\/www.eetimes.com\/siemens-acquires-ultrasoc-for-soc-lifecycle-product-suite\/\">&#8220;Siemens Acquires UltraSoC for SoC Lifecycle Product Suite&#8221;<\/a>. EE Times. Retrieved 12 July 2023.<\/em><\/li>\n<\/ol>\n\n\n\n<h3 class=\"wp-block-heading\">3.2 \u4e2d\u6587\u8bcd\u6761\u5f15\u7528\u5217\u8868<\/h3>\n\n\n\n<ol class=\"has-small-font-size wp-block-list\">\n<li>\u00b7&nbsp; <em>RISC-V<\/em><em>\u8b80\u5361\u5668\uff1a\u958b\u653e\u5f0f\u67b6\u69cb\u5730\u5716\u96c6\u7b2c1\u671f 1st. Strawberry Canyon. <a href=\"https:\/\/zh.wikipedia.org\/wiki\/Special:%E7%BD%91%E7%BB%9C%E4%B9%A6%E6%BA%90\/978-0999249109\">ISBN&nbsp;978-0999249109<\/a>.<\/em>)<\/li>\n\n\n\n<li>\u00b7&nbsp; <a href=\"https:\/\/t.cj.sina.com.cn\/articles\/view\/5703921756\/153faf05c01900gt8p\">\u65b0\u6d6a-\u56fe\u7075\u5956\u5f97\u4e3b\u52a0\u5165\u6e05\u534e\uff0c\u7275\u5934\u63a8\u52a8\u82af\u7247\u5f00\u6e90<\/a><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Celio, Christopher. <a href=\"https:\/\/github.com\/ucb-bar\/riscv-sodor\">ucb-bar\/riscv-sodor<\/a>. Regents of the University of California. [12 February 2015]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20180611023547\/https:\/github.com\/ucb-bar\/riscv-sodor\">\u5b58\u6863<\/a>\u4e8e2018-06-11\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Celio, Christopher. <a href=\"https:\/\/web.archive.org\/web\/20160623234620\/http:\/www-inst.eecs.berkeley.edu\/~cs152\/sp14\/handouts\/lab3.pdf\">CS 152 Laboratory Exercise 3<\/a> <\/em><em>(PDF)<\/em><em>. Regents of the University of California. [12 February 2015]. <\/em><em>\uff08<a href=\"http:\/\/www-inst.eecs.berkeley.edu\/~cs152\/sp14\/handouts\/lab3.pdf\">\u539f\u59cb\u5185\u5bb9<\/a> <\/em><em>(PDF)<\/em><em>\u5b58\u6863\u4e8e2016-06-23\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20170824175657\/https:\/semiaccurate.com\/2013\/08\/07\/a-long-look-at-how-arm-licenses-chips\/\">\u8a73\u7d30\u4e86\u89e3ARM\u8a31\u53ef\u82af\u7247\u7684\u65b9\u6cd5\uff1a\u7b2c1\u90e8\u5206<\/a><\/em><em>. <\/em><em>SemiAccurate. 2013 [2017-08-28]. <\/em><em>\uff08<a href=\"http:\/\/semiaccurate.com\/2013\/08\/07\/a-long-look-at-how-arm-licenses-chips\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2017-08-24\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"http:\/\/dl.acm.org\/citation.cfm?id=641917\">\u7cbe\u7c21\u6307\u4ee4\u96c6\u8a08\u7b97\u6a5f\u7684\u6848\u4f8b<\/a><\/em><em>. <\/em><em>ACM SIGARCH<\/em><em>\u8ba1\u7b97\u673a\u4f53\u7cfb\u7ed3\u6784\u65b0\u95fb. 1980\u5e7410\u6708, <strong>8<\/strong> (6): 25. <a href=\"https:\/\/dx.doi.org\/10.1145%2F641914.641917\">doi:10.1145\/641914.641917<\/a>.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/riscv.org\/members\/\">https:\/\/riscv.org\/members\/<\/a>. [2021-05-01]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20210426212215\/https:\/riscv.org\/members\/\">\u5b58\u6863<\/a>\u4e8e2021-04-26\uff09.<\/em> \u7f3a\u5c11\u6216|title=\u4e3a\u7a7a (<a href=\"https:\/\/zh.wikipedia.org\/wiki\/Help:%E5%BC%95%E6%96%87%E6%A0%BC%E5%BC%8F1%E9%94%99%E8%AF%AF#citation_missing_title\">\u5e2e\u52a9<\/a>)<\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20220428032908\/https:\/www.reuters.com\/article\/us-usa-china-semiconductors-insight-idUSKBN1XZ16L\">U.S.-based chip-tech group moving to Switzerland over trade curb fears<\/a>. Reuters. 2019-11-26 [2019-11-26]. <\/em><em>\uff08<a href=\"https:\/\/www.reuters.com\/article\/us-usa-china-semiconductors-insight-idUSKBN1XZ16L\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2022-04-28\uff09 <\/em><strong><em>\uff08\u82f1\u8bed\uff09<\/em><\/strong><em>.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20200415014905\/https:\/riscv.org\/risc-v-history\/#international\">RISC-V History &#8211; RISC-V International<\/a>. RISC-V International. [2020-05-14]. <\/em><em>\uff08<a href=\"https:\/\/riscv.org\/risc-v-history\/#international\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2020-04-15\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Krste Asanovi<\/em><em>\u0107<\/em><em>, David A. Patterson. <a href=\"https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2014\/EECS-2014-146.pdf\">Instruction Sets Should Be Free: The Case For RISC-V<\/a> <\/em><em>(PDF)<\/em><em>. U.C. Berkeley Technical Reports. [2018-10-31]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20190423083613\/https:\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2014\/EECS-2014-146.pdf\">\u5b58\u6863<\/a> <\/em><em>(PDF)<\/em><em>\u4e8e2019-04-23\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew; Asanovi<\/em><em>\u0107<\/em><em>, Krste. <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2017\/05\/riscv-spec-v2.2.pdf\">The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2<\/a> <\/em><em>(PDF)<\/em><em>. RISC-V International. 7 May 2017 [5 November 2021]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230413213242\/https:\/riscv.org\/wp-content\/uploads\/2017\/05\/riscv-spec-v2.2.pdf\">\u5b58\u6863<\/a> <\/em><em>(PDF)<\/em><em>\u4e8e2023-04-13\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew; Asanovi<\/em><em>\u0107<\/em><em>, Krste. <a href=\"https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/download\/Priv-v1.12\/riscv-privileged-20211203.pdf\">The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203<\/a> <\/em><em>(PDF)<\/em><em>. RISC-V International. 3 December 2021 [5 November 2021].<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Celio, Christopher. <a href=\"https:\/\/github.com\/ucb-bar\/riscv-boom\/\">riscv-boom<\/a>. GitHub. Regents of the University of California. [11 November 2016]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20180611025842\/https:\/github.com\/ucb-bar\/riscv-boom\">\u5b58\u6863<\/a>\u4e8e2018-06-11\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Asanovic, Krste; et al. <a href=\"https:\/\/github.com\/ucb-bar\/rocket-chip\">rocket-chip<\/a>. GitHub. The RISC-V Foundation. [11 November 2016]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20150403085654\/https:\/github.com\/ucb-bar\/rocket-chip\">\u5b58\u6863<\/a>\u4e8e2015-04-03\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Traber, Andreas; et al. <a href=\"https:\/\/www.pulp-platform.org\/\">PULP:Parallel Ultra Low Power<\/a>. ETH Zurich, University of Bologna. [5 August 2016]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230121061314\/https:\/www.pulp-platform.org\/\">\u5b58\u6863<\/a>\u4e8e2023-01-21\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/wiki.freebsd.org\/riscv\">FreeBSD Wiki: RISC-V<\/a>. [2018-11-11]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20180825002552\/https:\/wiki.freebsd.org\/riscv\">\u5b58\u6863<\/a>\u4e8e2018-08-25\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/freebsdfoundation.blogspot.be\/2016\/02\/initial-freebsd-risc-v-architecture.html\">FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed<\/a>. [2018-11-11]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20180404073012\/https:\/freebsdfoundation.blogspot.be\/2016\/02\/initial-freebsd-risc-v-architecture.html\">\u5b58\u6863<\/a>\u4e8e2018-04-04\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Montezelo, Manuel. <a href=\"https:\/\/groups.google.com\/a\/groups.riscv.org\/forum\/#!msg\/sw-dev\/u4VcUtB9r94\/4HiFYBhXAAAJ\">Debian GNU\/Linux port for RISC-V 64<\/a>. Google Groups. Google. [19 July 2018]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20181112180034\/https:\/groups.google.com\/a\/groups.riscv.org\/forum\/#!msg\/sw-dev\/u4VcUtB9r94\/4HiFYBhXAAAJ\">\u5b58\u6863<\/a>\u4e8e2018-11-12\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/fedoraproject.org\/wiki\/Architectures\/RISC-V\">Architectures\/RISC-V<\/a>. Fedora WIKI. Red Hat. [26 September 2016]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20210124044605\/https:\/fedoraproject.org\/wiki\/Architectures\/RISC-V\">\u5b58\u6863<\/a>\u4e8e2021-01-24\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em>Begari, Padmarao. <a href=\"https:\/\/groups.google.com\/a\/groups.riscv.org\/forum\/#!topic\/sw-dev\/j63wzz2ylY8\">U-Boot port on RISC-V 32-bit is available<\/a>. Google Groups. Microsemi. [15 February 2017]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20181112180034\/https:\/groups.google.com\/a\/groups.riscv.org\/forum\/#!topic\/sw-dev\/j63wzz2ylY8\">\u5b58\u6863<\/a>\u4e8e2018-11-12\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Almatary, Hesham. <a href=\"https:\/\/docs.sel4.systems\/Hardware\/RISCV.html\">RISC-V, seL4<\/a>. seL4 Documentation. CSIRO. [13 July 2018]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230118185256\/https:\/docs.sel4.systems\/Hardware\/RISCV.html\">\u5b58\u6863<\/a>\u4e8e2023-01-18\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20181111215351\/https:\/riscv.org\/software-tools\/riscv-angel\/\">riscv-angel<\/a>. The RISC-V Foundation. [2018-11-11]. <\/em><em>\uff08<a href=\"https:\/\/riscv.org\/software-tools\/riscv-angel\/\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2018-11-11\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew. <a href=\"http:\/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/2011\/EECS-2011-63.html\">Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed<\/a>. U.C. Berkeley: Regents of the University of California. 13 May 2011: 32 [25 August 2014]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20140826114558\/http:\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/2011\/EECS-2011-63.html\">\u5b58\u6863<\/a>\u4e8e2014-08-26\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em>Waterman, Andrew; et al. <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2015\/11\/riscv-compressed-spec-v1.9.pdf\">The RISC-V Compressed Instruction Set Manual Version 1.9 (draft)<\/a> <\/em><em>(PDF)<\/em><em>. RISC-V. [18 July 2016]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20161108041353\/https:\/riscv.org\/wp-content\/uploads\/2015\/11\/riscv-compressed-spec-v1.9.pdf\">\u5b58\u6863<\/a> <\/em><em>(PDF)<\/em><em>\u4e8e2016-11-08\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.solidot.org\/story?sid=61487\">\u963f\u91cc\u5df4\u5df4\u53d1\u5e03\u9996\u6b3e RISC-V \u5904\u7406\u5668<\/a>. <\/em><em>\u79d1\u6280\u884c\u8005. [2019-07-25]. \uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20190725102020\/https:\/www.solidot.org\/story?sid=61487\">\u5b58\u6863<\/a>\u4e8e2019-07-25\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/github.com\/T-head-Semi\/openc910\">openc910<\/a>. Github. [2023-01-10]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230110105039\/https:\/github.com\/T-head-Semi\/openc910\">\u5b58\u6863<\/a>\u4e8e2023-01-10\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/github.com\/isrc-cas\/c910-llvm\">c910-llvm<\/a>. Github. [2023-01-10]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230110105036\/https:\/github.com\/isrc-cas\/c910-llvm\">\u5b58\u6863<\/a>\u4e8e2023-01-10\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/www.sifive.com\/risc-v-core-ip\">RISC-V Portfolio: SiFive Processors<\/a>. SiFive. [2023-01-04]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230108055045\/https:\/www.sifive.com\/risc-v-core-ip\">\u5b58\u6863<\/a>\u4e8e2023-01-08\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"http:\/\/www.andestech.com\/tw\/%E7%94%A2%E5%93%81%E8%88%87%E8%A7%A3%E6%B1%BA%E6%96%B9%E6%A1%88\/\">\u7522\u54c1\u8207\u89e3\u6c7a\u65b9\u6848<\/a>. Andes Technology. [2023-07-28]. <\/em><em>\uff08\u539f\u59cb\u5185\u5bb9<a href=\"https:\/\/web.archive.org\/web\/20230728015526\/http:\/www.andestech.com\/tw\/%e7%94%a2%e5%93%81%e8%88%87%e8%a7%a3%e6%b1%ba%e6%96%b9%e6%a1%88\/\">\u5b58\u6863<\/a>\u4e8e2023-07-28\uff09 <\/em><strong><em>\uff08\u4e2d\u6587\uff08\u53f0\u6e7e\uff09\uff09<\/em><\/strong><em>.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/web.archive.org\/web\/20210724193151\/https:\/github.com\/OpenXiangShan\/XiangShan\">\u9999\u5c71\u958b\u6e90\u9805\u76ee<\/a>. [2021-07-06]. <\/em><em>\uff08<a href=\"https:\/\/github.com\/OpenXiangShan\/XiangShan\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2021-07-24\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/web.archive.org\/web\/20210723125230\/https:\/www.theregister.com\/2021\/07\/06\/xiangshan_risc_v\/\">Chinese chip designers hope to topple Arm&#8217;s Cortex-A76 with XiangShan RISC-V design<\/a>. [2021-07-06]. <\/em><em>\uff08<a href=\"https:\/\/www.theregister.com\/2021\/07\/06\/xiangshan_risc_v\/\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2021-07-23\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7 &nbsp;<em><a href=\"https:\/\/web.archive.org\/web\/20210706083613\/https:\/raw.githubusercontent.com\/OpenXiangShan\/XiangShan-doc\/main\/slides\/20210622-RVWC-%E9%A6%99%E5%B1%B1%E5%BC%80%E6%BA%90%E9%AB%98%E6%80%A7%E8%83%BDRISC-V%E5%A4%84%E7%90%86%E5%99%A8.pdf\">\u9999\u5c71\uff1a\u5f00\u6e90\u9ad8\u6027\u80fdRISC-V\u5904\u7406\u5668<\/a> <\/em><em>(PDF)<\/em><em>. [2022-05-16]. <\/em><em>\uff08<a href=\"https:\/\/raw.githubusercontent.com\/OpenXiangShan\/XiangShan-doc\/main\/slides\/20210622-RVWC-%E9%A6%99%E5%B1%B1%E5%BC%80%E6%BA%90%E9%AB%98%E6%80%A7%E8%83%BDRISC-V%E5%A4%84%E7%90%86%E5%99%A8.pdf\">\u539f\u59cb\u5185\u5bb9<\/a> <\/em><em>(PDF)<\/em><em>\u5b58\u6863\u4e8e2021-07-06\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20220507034208\/https:\/github.com\/chipsalliance\/Cores-SweRV\">Cores-SweRV \u958b\u6e90\u9805\u76ee<\/a>. [2021-09-25]. <\/em><em>\uff08<a href=\"https:\/\/github.com\/chipsalliance\/Cores-SweRV\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2022-05-07\uff09.<\/em><\/li>\n\n\n\n<li>\u00b7&nbsp; <em><a href=\"https:\/\/web.archive.org\/web\/20210925161552\/https:\/www.forbes.com\/sites\/tomcoughlin\/2020\/12\/14\/risc-v-and-marvell-technologies-advances-enable-storage-solutions\/\">RISC-V And Marvell Technologies Advances Enable Storage Solutions<\/a>. [2021-09-25]. <\/em><em>\uff08<a href=\"https:\/\/www.forbes.com\/sites\/tomcoughlin\/2020\/12\/14\/risc-v-and-marvell-technologies-advances-enable-storage-solutions\/\">\u539f\u59cb\u5185\u5bb9<\/a>\u5b58\u6863\u4e8e2021-09-25\uff09.<\/em><\/li>\n<\/ol>\n\n\n\n<h2 class=\"wp-block-heading\">4. \u5ef6\u4f38\u9605\u8bfb Further Reading<\/h2>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td><a href=\"https:\/\/en.wikipedia.org\/wiki\/Wikipedia:The_Wikipedia_Library\">Library resources<\/a> about <strong>RISC-V<\/strong>\uff08\u5173\u4e8eRISC-V\u7684\u5e93\u8d44\u6e90\uff09<\/td><\/tr><tr><td><a href=\"https:\/\/ftl.toolforge.org\/cgi-bin\/ftl?st=wp&amp;su=RISC-V\">Resources in your library<\/a> <a href=\"https:\/\/ftl.toolforge.org\/cgi-bin\/ftl?st=wp&amp;su=RISC-V&amp;library=0CHOOSE0\">Resources in other libraries<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/riscv.org\/technical\/specifications\/\">&#8220;The RISC-V Instruction Set Manual&#8221;<\/a>. RISC-V International.<\/li>\n<\/ul>\n\n\n\n<ul class=\"has-small-font-size wp-block-list\">\n<li><a href=\"https:\/\/github.com\/johnwinans\/rvalp\">&#8220;RISC-V Assembly Language Programming&#8221;<\/a>. <em>GitHub<\/em>. 8 November 2019.<\/li>\n\n\n\n<li>Waterman, Andrew (January 2016). <a href=\"https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-1.pdf\">&#8220;Design of the RISC-V Instruction Set Architecture&#8221;<\/a> (PDF). <em>EECS Department, University of California, Berkeley<\/em>. EECS-2016-1.<\/li>\n\n\n\n<li><a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a>; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">Patterson, David A.<\/a> (6 August 2014). <a href=\"https:\/\/www.eecs.berkeley.edu\/Pubs\/TechRpts\/2014\/EECS-2014-146.html\">&#8220;Instruction Sets Should Be Free: The Case For RISC-V&#8221;<\/a>. <em>EECS Department, University of California, Berkeley<\/em>. UCB\/EECS-2014-146.<\/li>\n\n\n\n<li>Waterman, Andrew; Lee, Yunsup; Avizienis, Rimas; Cook, Henry; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">Patterson, David A.<\/a>; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (25\u201327 August 2013). <a href=\"https:\/\/www.hotchips.org\/wp-content\/uploads\/hc_archives\/hc25\/HC25-posters\/HC25.26.p70-RISC-V-Warterman-UCB.pdf\"><em>The RISC-V Instruction Set<\/em><\/a> (PDF). <a href=\"https:\/\/www.hotchips.org\/archives\/2010s\/hc25\/\">Hot Chips 25<\/a>. Stanford University, Palo Alto, California, USA.<\/li>\n\n\n\n<li>Dabbelt, Palmer (7\u201311 February 2015). <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2015\/02\/riscv-software-toolchain-tutorial-hpca2015.pdf\"><em>RISC-V Software Ecosystem<\/em><\/a> (PDF). <a href=\"http:\/\/darksilicon.org\/hpca\/\">High-Performance Computer Architecture (HPCA) 2015<\/a>. San Francisco, California, USA.<\/li>\n\n\n\n<li>Lee, Yunsup (7\u201311 February 2015). <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2015\/02\/riscv-rocket-chip-generator-tutorial-hpca2015.pdf\"><em>RISC-V &#8220;Rocket Chip&#8221; SoC Generator in Chisel<\/em><\/a> (PDF). <a href=\"http:\/\/darksilicon.org\/hpca\/\">High-Performance Computer Architecture (HPCA) 2015<\/a>. San Francisco, California, USA.<\/li>\n\n\n\n<li>Waterman, Andrew; Lee, Yunsup; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">Patterson, David A.<\/a>; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (5 November 2015). <a href=\"https:\/\/riscv.org\/wp-content\/uploads\/2015\/11\/riscv-compressed-spec-v1.9.pdf\">&#8220;The RISC-V Compressed Instruction Set Manual Version 1.9 (draft)&#8221;<\/a> (PDF). <em>RISC-V<\/em>.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">5. \u5916\u90e8\u94fe\u63a5<\/h2>\n\n\n\n<div class=\"wp-block-media-text is-stacked-on-mobile\" style=\"grid-template-columns:15% auto\"><figure class=\"wp-block-media-text__media\"><img decoding=\"async\" src=\"https:\/\/upload.wikimedia.org\/wikipedia\/en\/thumb\/4\/4a\/Commons-logo.svg\/30px-Commons-logo.svg.png\" alt=\"\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p>Wikimedia Commons has media related to <strong><em><a href=\"https:\/\/commons.wikimedia.org\/wiki\/Category:RISC-V\">RISC-V<\/a><\/em><\/strong>.\uff08\u7ef4\u57fa\u5171\u4eab\u8d44\u6e90\u6709\u4e0eRISC-V\u76f8\u5173\u7684\u5a92\u4f53\u3002\uff09<\/p>\n<\/div><\/div>\n\n\n\n<ul class=\"has-small-font-size wp-block-list\">\n<li><a href=\"https:\/\/riscv.org\/\">Official website<\/a> <a href=\"https:\/\/www.wikidata.org\/wiki\/Q17637401#P856\"><\/a>\uff08\u5b98\u65b9\u7f51\u7ad9\uff09<\/li>\n\n\n\n<li><a href=\"https:\/\/github.com\/jameslzhu\/riscv-card\">RISC-V Instruction Set Reference Card<\/a> on <a href=\"https:\/\/en.wikipedia.org\/wiki\/GitHub\">GitHub<\/a> \uff08GitHub\u4e0a\u7684RISC-V\u6307\u4ee4\u96c6\u53c2\u8003\u5361\uff09<\/li>\n\n\n\n<li><a href=\"https:\/\/www.eetimes.com\/risc-v-an-open-standard-for-socs\/\">&#8220;RISC-V: An Open Standard for SoCs&#8221;<\/a>. <em>EETimes<\/em>. 8 July 2014.\uff08RISC-V: soc\u7684\u5f00\u653e\u6807\u51c6\u3002EETimes\u30022014\u5e747\u67088\u65e5\u3002\uff09<\/li>\n\n\n\n<li><a href=\"http:\/\/www.adapteva.com\/andreas-blog\/analyzing-the-risc-v-instruction-set-architecture\/\">&#8220;Analyzing the RISC-V Instruction Set Architecture&#8221;<\/a>. <em><a href=\"https:\/\/en.wikipedia.org\/wiki\/Adapteva\">Adapteva<\/a><\/em>. 11 August 2014.\uff08RISC-V\u6307\u4ee4\u96c6\u67b6\u6784\u5206\u6790\u30022014\u5e748\u670811\u65e5\u3002\uff09<\/li>\n\n\n\n<li>Celio, Christopher; Dabbelt, Palmer; <a href=\"https:\/\/en.wikipedia.org\/wiki\/David_Patterson_(computer_scientist)\">Patterson, David A.<\/a>; <a href=\"https:\/\/en.wikipedia.org\/wiki\/Krste_Asanovi%C4%87\">Asanovi\u0107, Krste<\/a> (8 July 2016). <em>The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V<\/em> (Technical report). University of California, Berkeley. <a href=\"https:\/\/en.wikipedia.org\/wiki\/ArXiv_(identifier)\">arXiv<\/a>:<a href=\"https:\/\/arxiv.org\/abs\/1607.02318\">1607.02318<\/a>. UCB\/EECS-2016-130.<br>\uff08Celio\uff0cChristopher\uff1bDabbelt\uff0cPalmer\uff1bPatterson\uff0cDavid A.\uff1bAsanovi\u0107\uff0cKrste\uff082016\u5e747\u67088\u65e5\uff09\u3002\u7cbe\u7b80\u6307\u4ee4\u96c6\u8ba1\u7b97\u673a\u7684\u66f4\u65b0\u6848\u4f8b\uff1a\u907f\u514dISA\u81a8\u80c0\uff0c\u4e3aRISC-V\u8fdb\u884c\u5b8f\u64cd\u4f5c\u878d\u5408\uff08\u6280\u672f\u62a5\u544a\uff09\u3002\u52a0\u5dde\u5927\u5b66\u4f2f\u514b\u5229\u5206\u6821\u3002arXiv\uff1a1607.02318\u3002UCB\/EECS-2016-130\u3002\uff09<\/li>\n\n\n\n<li><a href=\"https:\/\/www.electromaker.io\/blog\/article\/what-is-risc-v\">&#8220;What is RISC-V?&#8221;<\/a>. <em>Electromaker<\/em>. 14 July 2021.\uff08\u201c\u4ec0\u4e48\u662fRISC-V?\u201dElectromaker, 2021\u5e747\u670814\u65e5\u3002\uff09<\/li>\n\n\n\n<li><a href=\"https:\/\/www.youtube.com\/channel\/UC5gLmcFuvdGbajs4VL-WU3g\">YouTube\u4e0a\u7684RISC-V\u9891\u9053<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>RISC-V\uff08\u53d1\u97f3\u4e3a\u201crisk-five\u201d\uff09 \u662f\u4e00\u4e2a\u57fa\u4e8e\u7cbe\u7b80\u6307\u4ee4\u96c6\uff08RISC\uff09\u539f\u5219\u7684\u5f00\u6e90\u6307\u4ee4\u96c6\u67b6\u6784\uff08ISA\uff09\uff0c\u7b80\u6613\u89e3\u91ca\u4e3a\u4e0e\u5f00\u6e90\u8f6f\u4ef6\u8fd0\u52a8\u76f8\u5bf9\u5e94\u7684\u4e00\u79cd\u201c\u5f00\u6e90\u786c\u4ef6\u201d\u3002\u8be5\u9879\u76ee\u4e8e2010\u5e74\u5728\u52a0\u5dde\u5927\u5b66\u4f2f\u514b\u5229\u5206\u6821\u542f\u52a8\uff0c\u4f46\u8bb8\u591a\u8d21\u732e\u8005\u662f\u8be5\u5927\u5b66\u4ee5\u5916\u7684\u5fd7\u613f\u8005\u548c\u884c\u4e1a\u5de5\u4f5c\u8005\u3002<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[56,47],"tags":[155,101],"class_list":["post-2273","post","type-post","status-publish","format-standard","hentry","category-open-source-movement","category-integrated-circuit-chip","tag-155","tag-101"],"_links":{"self":[{"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/posts\/2273","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/comments?post=2273"}],"version-history":[{"count":0,"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/posts\/2273\/revisions"}],"wp:attachment":[{"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/media?parent=2273"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/categories?post=2273"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cathayvista.top\/index.php\/wp-json\/wp\/v2\/tags?post=2273"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}